This application claims the benefit of the Korean Application No. P 2002-5150 filed on Jan. 29, 2002, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly, to an apparatus and method for driving a ferroelectric memory that can secure enough read/write cycle time of a corresponding address when a chip is driven.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM), becomes the center of attention as the next-generation memory device since it has a data processing speed of the dynamic random access memory (DRAM) grade and preserves stored data even if the power is off.
The FRAM is a memory device having a similar structure to the DRAM, and uses a high residual dielectric polarization that is the characteristic of a ferroelectric material that is used as a material of a capacitor in the memory device.
Due to the characteristic of the residual dielectric polarization, the data stored in the memory device is not erased even if an applied electric field is removed.
FIG. 1 is a characteristic diagram illustrating the hysteresis loop of a general ferroelectric material.
As shown in FIG. 1, even though the electric field is removed, the polarization induced by the electric field does not vanish due to the existence of the residual dielectric polarization (or spontaneous polarization), but is kept a specified amount (i.e., states d and a).
In the nonvolatile ferroelectric memory cell, the states d and a can correspond to 1 and 0, respectively, and this characteristic enables the cell to be used as a memory device.
Hereinafter, the conventional nonvolatile ferroelectric memory device will be explained with reference to the accompanying drawings.
FIG. 2 is a view illustrating the construction of a unit cell of the conventional nonvolatile ferroelectric memory device.
As shown in FIG. 2, the unit cell of the conventional nonvolatile ferroelectric memory cell includes a bit line B/L formed in one direction, a word line W/L formed in a direction crossing the bit line B/L, a plate line P/L formed in the same direction as the word line W/L at a specified distance from the word line W/L, a transistor T1 whose gate is connected to the word line W/L and whose source is connected to the bit line B/L, and a ferroelectric capacitor FC1 whose first terminal is connected to a drain of the transistor T and whose second terminal is connected to the plate line P/L.
The data input/output operations of the non-volatile ferroelectric memory device are as follows.
FIG. 3A is a timing diagram illustrating an operation of a write mode of a common non-volatile ferroelectric memory device. FIG. 3B is a timing diagram illustrating an operation of a read mode.
In the case of the write mode, when a chip enable signal CSBpad applied from the outside is activated from high to low and a write enable signal WEBpad is applied from high to low, the write mode begins.
When address decoding begins in the write mode, a pulse applied to a corresponding word line is transited from low to high and a cell is selected.
In a period where the word line maintains a high state, a uniform period of high signal and a uniform period of low signal are sequentially applied to a corresponding plate line. In order to write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d to a selected cell, a xe2x80x9chighxe2x80x9d or xe2x80x9clowxe2x80x9d signal synchronized with the write enable signal WEBpad is applied to a corresponding bit line.
That is, when a high signal is applied to the bit line and when a signal applied to the plate line is at a low state in a period where a signal applied to the word line is at a high state, a logic value xe2x80x9c1xe2x80x9d is recorded in a ferroelectric capacitor. When a low signal is applied to the bit line and a signal applied to the plate line is a high signal, a logic valuexe2x80x9c0xe2x80x9d is recorded in the ferroelectric capacitor.
An operation of reading data stored in a cell is as follows.
When the chip enable signal CSBpad is activated from high to low from the outside, all of the bit lines are equipotentialized to a low voltage by an equalizing signal before a corresponding word line is selected.
After the respective bit lines are deactivated, the address is decoded and a low signal is transited to a high signal in a corresponding word line by a decoded address, to thus select a corresponding cell. Data Qs corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric memory is destroyed by applying a high signal to the plate line of a selected cell.
If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, data Qns corresponding to the logic value xe2x80x9c0xe2x80x9d is not damaged. Accordingly, destroyed data and the data that is not destroyed output different values by the above-mentioned principle of the hysteresis loop. Therefore, a sense amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
That is, when data is destroyed, a state is changed from d to f like in the hysteresis loop of FIG. 1. When data is not destroyed, a state is changed from a to f. Therefore, when the sense amplifier is enabled after a uniform time passes, data is amplified, to thus output the logic value xe2x80x9c1xe2x80x9d. When data is not destroyed, data is amplified and the logic value xe2x80x9c0xe2x80x9d is output.
After the data is amplified through the sense amplifier, the plate line is deactivated from high to low in a state where a high signal is applied to a corresponding word line because the data must be recovered to original data.
In the ferroelectric memory performing the read/write operation, when an address is changed and a new address is set, an enough time for completing a normal read/write operation by a corresponding address is required.
That is, when a corresponding address period is smaller than a cycle time, memory cell data may be damaged.
However, such a conventional ferroelectric memory has the following problem.
An enough time for completing a normal read/write operation by a corresponding address is required. However, in a conventional technology, when a different address comes, it is not possible to intercept the address. Accordingly, the cycle time of the corresponding address is not guaranteed.
When the cycle time of the corresponding address is not guaranteed, address short pulse noise is generated to affect a chip operation and to damage data.
Accordingly, the present invention is directed to an apparatus and method for driving a ferroelectric memory that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an apparatus and method for driving a ferroelectric memory that can secure an enough read/write cycle time of a corresponding address during when a chip is driven.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve the object and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the present invention provides an apparatus for driving a ferroelectric memory in a driving circuit that generates an operation pulse for controlling operation of a ferroelectric chip, the apparatus including an address latch block for latching a buffered address signal by a feedback cell operation pulse, an address transition detection summation ATDSUM value outputting block for generating an address transition detection pulse (ATD) signal by detecting change of an address signal, and for outputting summation of address transition pulses ATDSUM generated by a plurality of addresses, a pulse width extension/control pulse generating block for extending a pulse width of the summation of the address transition pulses ATDSUM and outputting a chip control pulse by using an extended signal, and a cell operation pulse generating block for generating a cell operating pulse with a pulse width required on a read/write chip operation by using the chip control pulse, wherein in an active region of the cell operation pulse corresponding to the address, an ATD SIGNAL of another address is not generated.
To achieve the object and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the present invention provides method for driving a ferroelectric memory in a case that one cycle time is divided into intervals of t0, t1, t2, t3, t4, and t5 in order to generate an operation pulse for controlling an operation of a ferroelectric chip, the method comprising the steps of a) generating an address transition detecting pulse (ATD) signal at a starting portion of the t1 period when an address transition is occurred at an end portion of the t0 period, b) summing the ATD and outputting the summed address transition detection pulse ATDSUM, and c) extending a pulse width of the summed address transition detection pulse ATDSUM so as for an end edge time thereof to extend to the t3 period and producing a control pulse CP by using the same. A cell operation pulse OP at from the t2 period to the t5 period according to the control pulse CP is produced so that a normal read/write operations is performed from the t2 period t5 period and generation of the address transition detection pulse (ATD) signal is intercepted though new address is entered into an active period of the cell operation pulse OP.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.